CXMT at 10% of DRAM Revenue: The DUV Anatomy of a Rise and Its EUV Ceiling

In Q2 2026, ChangXin Memory Technologies (CXMT) captured 10% of global DRAM revenue — the first time a Chinese memory maker has crossed the double-digit line in a market three companies have controlled for three decades¹. Counterpoint Research and UBS had earlier projected that CXMT would not reach the 10% range before 2028; the company cleared it in quarterly revenue roughly two years ahead of that schedule². The knee-jerk read is that Chinese DRAM has caught up. The correct read is stranger: a manufacturer with no access to EUV lithography, a cost per bit more than 30% above the leaders, and HBM yields modeled around 25% just printed a double-digit revenue share — because the leaders handed it the market.

This guide decomposes both halves in order: the silicon (how you build sub-12nm-class DRAM with 193nm light), and the economics (what the 10% actually earns, and what it cannot). Every number below was checked at its primary source; every calculation actually runs.

The 4-5-8-8-10 Series, Correctly Read

Counterpoint's quarterly table reads 4% (Q2 2025), 5% (Q3 2025), 8% (Q4 2025), 8% (Q1 2026), 10% (Q2 2026)¹. Six percentage points of revenue share in four quarters. TrendForce's own tally puts CXMT fourth at 9.5% for the same quarter, behind Samsung at 39.4%, SK hynix at 24.9%, and Micron at 23.3%³ — the half-point spread between the two trackers is methodology, not disagreement.

sh = [4, 5, 8, 8, 10]  # Counterpoint, DRAM revenue share 2Q25 -> 2Q26, pct points
print("Quarterly series:", sh)
print("QoQ deltas (pp):", [sh[i+1] - sh[i] for i in range(4)])
print("YoY gain 2Q25->2Q26:", sh[-1] - sh[0], "pp")
print("Pace:", (sh[-1]-sh[0]) / 4, "pp/quarter")
print("Linear extrapolation to 15%:", round(5 / ((sh[-1]-sh[0]) / 4), 1), "quarters after 2Q26")
print("UBS/Counterpoint 2028 shipment-share forecast; 10% revenue arrived 2Q26,")
print("i.e. roughly 8-12 quarters early, with the shipment-vs-revenue caveat.")

Quarterly series: [4, 5, 8, 8, 10]
QoQ deltas (pp): [1, 3, 0, 2]
YoY gain 2Q25->2Q26: 6 pp
Pace: 1.5 pp/quarter
Linear extrapolation to 15%: 3.3 quarters after 2Q26
UBS/Counterpoint 2028 shipment-share forecast; 10% revenue arrived 2Q26,
i.e. roughly 8-12 quarters early, with the shipment-vs-revenue caveat.

Two caveats before the celebration. First, the 2028 projections were about shipment share; revenue share is flattered by an abnormal market — global DRAM revenue grew 57% quarter-over-quarter in Q2 2026 and 385% year-over-year, while CXMT's own revenue surged some 716% YoY⁴. Second, the share gain is not a head-to-head win. Samsung and SK hynix deliberately redirected capacity toward 1c DRAM and HBM for AI accelerators, tightening supply in legacy consumer-server niches like DDR4 and up to 1a/1b-class DDR5, leaving a vacuum that CXMT filled at its DUV nodes². CXMT's rise is, in the precise sense, parasitic on the leaders' HBM pivot. That is a strength while the pivot lasts and a vulnerability the moment it reverses.

Counterpoint's own framing agrees: fifteen percent is the survival threshold CXMT must cross to secure investment funds, in the words of Counterpoint director Hwang Min-sung, and "all of its current investments are a race to reach that goal first"². Capacity follows: from about 320,000 wafers per month today to 420,000 next year, with a plan to double current levels by 2030².

Silicon First: How You Ship 11.95nm Half-Pitch Without EUV

At the 2026 World Manufacturing Convention in Hefei, CXMT announced mass production of its fifth-generation DRAM platform, G5. The headline figure: an active-area half-pitch of 11.95 nanometers in the memory array⁵⁶.

Why half-pitch rather than a node name? Node names ("1b", "1c", "G5") are marketing labels each vendor defines for itself; half-pitch — half the distance between the repeating lines of memory cells — is a physical measurement you can put under a microscope. CXMT's 11.95nm half-pitch equals a full pitch of about 23.9nm, which lands inside the roughly 22-26nm active-area pitch range Semiconductor Engineering cites for 1b-class DRAM — a generation Samsung and SK hynix already run in volume⁷. So G5 is an honest 1b-class platform, "rivaling the industry's best mass-produced nodes" in CXMT's phrasing, not the 1c class Samsung and SK hynix build with EUV.

Getting there without EUV means self-aligned quadruple patterning (SAQP). The idea: a single 193nm DUV immersion exposure defines a sparse set of "mandrel" lines; then alternating cycles of deposition and etch multiply them — deposit a spacer layer over the mandrel, etch it back so only sidewalls remain, remove the mandrel, and the sidewalls themselves become the mask. Each mandrel line turns into two or four final lines, so one lithographic pass yields features finer than the light can print directly.

The critical property is self-alignment: the final line positions are defined by the spacers, all at once, in a single deposition step — not by four separate lithography exposures trying to land on the same spot. Compare litho-etch-litho-etch quadruple patterning, where every exposure must overlay the previous ones within a tight error budget, and the errors stack. SAQP trades overlay error for a different pathologies: variations in deposition thickness, etch profile, or the initial mandrel pattern accumulate across the steps, producing uneven line spacing the industry calls pitch walk⁷. CXMT's +50% die-per-wafer claim against its own previous generation⁶ rests on controlling that walk — and the company has disclosed no yield figures for G5⁷.

The G5 platform pairs SAQP with two more silicon decisions worth naming. The array capacitor reaches a depth-to-width (aspect) ratio of 45:1, which CXMT credits to a reworked process flow and new materials⁵⁸. That number matters because the DRAM cell stores its bit as charge on that capacitor: the taller and skinnier the structure, the more capacitance you keep on a tighter footprint — but a 45:1 trench is a ferocious etch and fill problem, and the deeper capacitors have historically suffered from leakage that forces more frequent refresh, trading density for power. CXMT also adapted high-k metal gate (HKMG) technology to DRAM, cutting core-area height to 6,762nm⁷⁵.

The Ceiling Is Not a Node Number. It Is a Timing Margin.

Here is the structural argument in one sentence: LPDDR6 moved the signaling to PAM3, and multi-patterning overlay noise eats exactly the timing margin PAM3 needs.

CXMT's LPDDR6 — in mass production since the end of August 2026, debuting in Xiaomi's 18 Fold with the XRING O3 SoC, at up to 12,800 Mbps on 16 Gb dies⁹¹⁰ — sits at 88.9% of SK hynix's 1c-EUV LPDDR6 at 14.4 Gbps¹¹¹². Not a huge gap. But the JEDEC LPDDR6 baseline is 10.7 Gbps; Samsung's ISSCC 2026 part runs 12.8 Gbps¹³. CXMT is at the level of Samsung's least aggressive bin, not the Korean ceiling.

The reason is not raw device speed — it is variation. NRZ (LPDDR5-generation signaling) encodes one bit per symbol: the eye is one large voltage window with generous timing tolerance. PAM3 encodes 1.58 bits per symbol across three levels, which compacts both the vertical margin between levels and the horizontal margin in time. A data eye that had to be divided into three distinguishable states tolerates far less edge-position jitter before the receiver mis-samples. And where does jitter come from on a DRAM die? Capacitance variation cell-to-cell, sense-amplifier mismatch, wordline resistance spread — all downstream of dimensional variation. Every SAQP pitch-walk nanometer on the array lands on the bitline capacitance distribution, which lands on the access-time distribution, which closes the PAM3 eye. The same overlay-error accumulation that SAQP minimizes but cannot eliminate is precisely the variable that PAM3 punishes. That is why the DUV ceiling shows up as a data-rate bin, not as a wafer that fails: CXMT ships the speed its variation distribution allows, EUV leaders ship the speed their lithography allows, and the difference is 12.8 versus 14.4 Gbps.

Economics First: The 30% Cost Wedge

SemiAnalysis, in its CXMT deep-dive, found CXMT's DDR5 cost per bit more than 30% above the three leading suppliers¹⁴. DUV multi-patterning is the direct driver: every SAQP deposition-etch cycle adds process steps, tool time, and yield presses — our derivation from that >30% cost-per-bit gap (the cell below indexes it at 1.30) is that CXMT needs roughly 30% more wafer starts for the same usable output. None of that mattered while a supply-compressed market set prices for everyone. Model it:

lc, cc = 1.0, 1.30   # indexed leader cost/bit; CXMT cost/bit (SemiAnalysis: >30% above leaders, DDR5)
for label, asp in [("normalized market, ASP 1.4x leader cost", 1.4),
                   ("boom pricing, ASP 3.0x leader cost", 3.0)]:
    lm = 100*(asp-lc)/asp; cm = 100*(asp-cc)/asp
    print(f"{label}: leader margin {lm:.0f}%, CXMT margin {cm:.0f}%, wedge {lm-cm:.0f} pp")
print(f"CXMT breakeven ASP: {cc:.2f}x leader cost; at that price leaders still earn {(cc-1)/cc*100:.0f}%")
print("Same usable output, +30% starts: 320K EUV-equivalent wpm needs", round(320*1.3), "K DUV starts;")
print("320K DUV wpm delivers", round(320/1.3), "K EUV-equivalent throughput.")

normalized market, ASP 1.4x leader cost: leader margin 29%, CXMT margin 7%, wedge 21 pp
boom pricing, ASP 3.0x leader cost: leader margin 67%, CXMT margin 57%, wedge 10 pp
CXMT breakeven ASP: 1.30x leader cost; at that price leaders still earn 23%
Same usable output, +30% starts: 320K EUV-equivalent wpm needs 416 K DUV starts;
320K DUV wpm delivers 246 K EUV-equivalent throughput.

The boom compresses the wedge from 21 points to 10 because the 30% cost penalty is fixed while the selling price triples. That is the mechanism behind CXMT's spectacular reported profitability — a gross margin above 70% in 1Q26 on SemiAnalysis's estimate¹⁴ — and the mechanism that reverses it. The moment commodity DRAM prices normalize toward leader cost plus normal margin, CXMT's margin does not merely shrink; it goes to roughly zero at an ASP where the leaders still earn 23%. CXMT is not a low-cost disruptor. It is a high-cost producer whose economics currently work because everyone's prices are being set by a shortage it did not cause.

EUV cannot be bought to close this. ASML is not permitted to ship EUV systems to Chinese customers⁷, so the gap is not versioning that a determined spend closes — it is a tooling embargo with no substitute vendor, and the DUV-minus-patterning route pays the 30% wedge indefinitely.

HBM: Two Generations Behind, Arithmetic to Match

The AI-memory market is where the revenue actually is, and here CXMT is the furthest behind. The Information reported in late August 2026 that CXMT has begun small-volume HBM3E production, with Alibaba's T-Head unit and Cambricon qualifying the silicon against their own processors, targeting commercial use as early as 2027¹⁵¹⁶. SK hynix has been mass-producing HBM3E since 2024; by 2026 the Korean leaders were in HBM4 and sampling HBM4E¹⁵. Two generations, on a product where the leaders' lead compounds through TSV stacking knowhow and MR-MUF-style assembly processes CXMT has not demonstrated at scale.

SemiAnalysis modeled CXMT's HBM3 eight-high stack yield around 25% — roughly 35% on the front end and 70% on the back end, combining to about one good stack in four⁴¹⁵.

fe, be = 0.35, 0.70   # SemiAnalysis-modeled HBM3 8-high: front-end / back-end yield
print("8-high stack yield:", round(fe*be, 3), "(~25% as reported)")
print("Cost multiplier per good stack:", round(1/(fe*be), 2), "x")
print("P(all 8 dies good, independent, no screening):", round(fe**8, 5))

8-high stack yield: 0.245 (~25% as reported)
Cost multiplier per good stack: 4.08 x
P(all 8 dies good, independent, no screening): 0.00023

That is why known-good-die (KGD) screening is non-negotiable in HBM: stack eight unscreened 35%-yield dies and you scrap 99.98% of stacks. Every layer must be tested before stacking, and each stacking pass then integrates over the survivors — 0.35 × 0.70, the 25% line. At that yield every good 8-high HBM3 stack carries roughly 4× the wafer-plus-TSV-plus-assembly cost of a stack from a mature producer, which is why CXMT's HBM3E is qualification silicon for domestic AI chips in a sanctioned market, not HBM exports.

The Capacity Check

Capacity plans — 320K to 420K wafers per month next year²¹⁷ — close the loop. As a sanity check on the share numbers, at an assumed 500 8-Gb-equivalent dies per 300mm wafer (our estimate, not a disclosed figure):

wpm, dpw = 420_000, 500   # dpw is OUR estimate (8Gb-equivalent, 300mm wafer)
print("Bit output estimate:", wpm * dpw * 8e9 / 8e15, "PB/month (ours, labeled)")
print("Note: real mix skews to 16Gb+ mobile/server dies; this is a scale check, not a forecast.")

Bit output estimate: 210.0 PB/month (ours, labeled)
Note: real mix skews to 16Gb+ mobile/server dies; this is a scale check, not a forecast.

210,000 TB per month of raw 8-Gb-equivalent bits is the right order of magnitude for a 10%-of-revenue player in an inflated-price market — and it inherits the 30%-more-starts penalty above: a meaningful fraction of those wafers exist only to buy back the yield and multi-pass cost of DUV.

What Would Falsify the Bull Case

The bearable-case-for-CXMT reads: they scale to 15%, HBM3E qualifies in 2027, LPDDR6 graduates from a single Xiaomi foldable (shipment target reportedly 200,000 to 300,000 units¹⁸) into a real product family, and the NAND R&D line Reuters reports CXMT is planning in Beijing³ becomes a second leg¹⁹. Three observations would falsify it, in descending order of decisiveness:

1. Commodity price normalization. If DDR4/DDR5 prices settle toward historic cost-plus-margin, the cost-wedge math above turns CXMT's margin to zero while the leaders coast. This is the single most probable falsifier — it requires no CXMT failure, only a normal market.
2. HBM qualification slipping past 2027. The T-Head and Cambricon qualification is unconfirmed publicly on the record by any party¹⁵; The Information's own sources put CXMT three to five years behind on HBM overall¹⁵. Volume HBM in 2027 already assumes flawless qualification of silicon whose modeled yields are 25%.
3. SAQP economics at 1c-class. If the pitch-walk problem worsens faster than deposition/etch control improves as CXMT pushes below the 1b class, the LPDDR6 speed bins gap widens beyond 12.8/14.4 and the NAND R&D line inherits the same tooling ceiling.

None of these is a China-sentiment question; all three are silicon and pricing questions. CXMT's Q2 2026 milestone is real, primary-verified, and genuinely historic — and it was purchased with other people's abandoned market, at a structural cost discount it cannot shed. Ten percent of revenue share in a shortage is not ten percent in a normal market. The next two quarters decide which of those CXMT actually owns.